The present invention relates to a semiconductor device and to a method of method of manufacture thereof; and, more particularly, the invention relates to a semiconductor device in which a semiconductor element has at least a stress cushioning layer and a semiconductor protective layer, and the end faces of these layers are positioned inside the cutting scribe lines formed on a semiconductor wafer, and the range of the surface at the end of the semiconductor element from the end face to the inside of the scribe line is exposed.
Recently, there has been an increasing demand for miniaturization and high performance in various electronic elements; and, in association with this demand, there have also been requests for a semiconductor device using electronic elements capable of speeding up information processing, as well as high density packing and high density assembly of the electron elements. Namely, in correspondence with these requests, there have been changes in the general character of a semiconductor device from the pin insertion type to the surface mounting type so as to increase the mounting density; and order to provide a multi-pin configuration, various packages from a DIP (dual inline package) to a QFP (quad flat package) or a PGA (pin grid array) have been developed.
However, in the QFP type package, the connection lead wires for connecting with the mounting substrate are centralized in the peripheral part of the package and the connection lead wires themselves are thin and deformable, so that, as the number of pins increases, the mounting becomes more difficult. In the PGA type package, the terminals to be connected to the mounting substrate are thin and long and a considerable number of terminals are centralized, so that high speed processing of information is difficult from the viewpoint of characteristics; and, moreover, the PGA arrangement is of a pin insertion type, so that surface mounting is not available, and it is disadvantageous in a high density assembly.
Recently, to solve various problems concerning these packages and to realize a semiconductor capable of high speed processing of information, a BGA (ball grid array) package having a stress cushioning layer between the semiconductor element and the substrate on which a wiring circuit is formed and a bump electrode which is an external terminal on the mounting substrate surface side of the substrate with the wiring circuit has been developed, and the details thereof are disclosed in the specification of U.S. Pat. No. 5,148,265. In the package described in the specification of U.S. Pat. No. 5,148,265, since the terminals to be connected to the mounting substrate are ball-shaped solder terminals, the lead wires are free of deformation, unlike the QFP type; and, since the terminals are scattered over the entire mounting surface, the pitch between the terminals is large and surface mounting can be carried out easily. The bump electrode which is an external terminal is shorter in length than that of the PGA type, so that the inductance component is decreased, and the information processing speed is increased, and high speed processing of information is made possible.
On the other hand, recently, in association with wide spread use of portable information terminals, there is an increasing demand for miniaturization and high density assembly of a semiconductor device. Therefore, recently, a CSP (chip scale package) having a package size that is almost equal to the chip size has been developed; and, for example, various types of CSPs are disclosed in “Nikkei Microelement” (pp. 38-64) issued by Nikkei BP, Ltd. (February 1998). CSPs disclosed in this publication are manufactured in such a way that semiconductor elements cut into pieces are bonded onto a polyimide or ceramics substrate on which a wiring layer is formed, and then the wiring layer and semiconductor elements are electrically connected, such as by wire bonding, single point bonding, gang bonding, or bump bonding, and the connections are sealed with resin, after which external terminals such as solder bumps are formed thereon.
In Japanese Patent Application Laid-Open 9-232256 and Japanese Patent Application Laid-Open 10-27827, methods for mass-producing CSPs are disclosed. These manufacturing methods form bumps on a semiconductor wafer, electrically connect a wiring substrate via the bumps, seal the connections with resin, form external electrodes on the wiring substrate, and finally cut the semiconductor wafer into pieces, thus producing individual semiconductor devices. Furthermore, “Nikkei Microelement” (p. 164 to p. 167) issued by Nikkei BP, Ltd. (April 1998) discloses another manufacturing method for mass-producing CSPs. This manufacturing method forms bumps by plating on a semiconductor wafer, seals the part other than the bumps with resin, forms external electrodes in the bumps, then cuts the semiconductor wafer into pieces, thus producing individual semiconductor devices. In addition, Japanese Patent Application Laid-Open 10-92865 discloses a semiconductor device of a type in which a resin layer for cushioning stress is installed between external electrodes and semiconductor elements. Individual semiconductor devices are manufactured by processing units of semiconductor wafers in a batch and finally cutting each semiconductor wafer into pieces.
The aforementioned semiconductor devices (semiconductor package) of the type in which a plurality of resin layers and external electrodes are formed in units of semiconductor wafers in a batch, and then each semiconductor wafer is cut (diced) into pieces, has a constitution such that the interfaces of a plurality of resin layers sequentially formed on each semiconductor wafer are exposed on the end face of each semiconductor package, so that when a large mechanical stress is applied to the interfaces of the plurality of resin layers at the time of dicing of the semiconductor wafer, or when a large thermal stress is applied to the interfaces of the plurality of resin layers due to sudden temperature changes at the time of mounting of the semiconductor package, the stress is centralized to the interfaces between the semiconductor element exposed on the end face of the semiconductor package and the plurality of resin layers, so that one or more of the plurality of resin layers are peeled off and the semiconductor package may be damaged.
As mentioned above, such a known semiconductor device cannot always exhibit high reliability, and it is difficult to obtain a high manufacturing yield rate.
The present invention was developed in view of the foregoing technical background and is intended to provide a semiconductor device, and a method of manufacture thereof, having high reliability and a satisfactory manufacturing yield rate, such that the constituent part to which a concentrated stress is applied at the time of cutting of a semiconductor wafer and at the time of mounting of a semiconductor device is improved so as to withstand the stress, whereby the occurrences of damage of the semiconductor devices due to applied stress are greatly reduced.
To accomplish the above object, the semiconductor device of the present invention has semiconductor elements obtained by cutting a semiconductor wafer, having an integrated circuit and an electrode pad formed on one side thereof, along a cutting scribe line; a stress cushioning layer installed on the semiconductor elements; a lead wire portion extending from the electrode pad to the top of the stress cushioning layer through an opening formed in the stress cushioning layer on the electrode pad; external electrodes arranged on the lead wire portion on the top of the stress cushioning layer; and a conductor protective layer installed on the stress cushioning layer, excluding the external electrode arranged portion; and a conductor portion. The stress cushioning layer, lead wire portion, conductor protective layer, and external electrodes have a means for forming each end face on the end surface of the semiconductor elements inside the cutting scribe line and exposing the range from the end face on the end surface of the semiconductor elements to the inside of the scribe line.
To accomplish the above object, the semiconductor device of the present invention has semiconductor elements obtained by cutting a semiconductor wafer, having an integrated circuit and an electrode pad formed on one side thereof, along the cutting scribe line; a semiconductor element protective layer installed on the semiconductor elements; a stress cushioning layer installed on the semiconductor element protective layer; a first opening formed in the semiconductor element protective layer on the electrode pad; a second opening formed in the stress cushioning layer on the electrode pad; a lead wire portion extending to the top of the stress cushioning layer through the first opening and second opening, respectively, from the electrode pad; external electrodes arranged on the lead wire portion on the top of the stress cushioning layer; and a conductor protective layer installed on the stress cushioning layer, excluding the external electrode arranged portion, and on the conductor portion. The semiconductor element protective layer, stress cushioning layer, lead wire portion, conductor protective layer, and external electrodes have a means for forming each end face on the end surface of the semiconductor elements inside the cutting scribe line and exposing the range from the end face on the end surface of the semiconductor elements to the inside of the scribe line.
To accomplish the above object, the semiconductor device manufacturing method of the present invention has a first step of forming a plurality of semiconductor elements having an integrated circuit and an electrode pad on the circuit forming surface of a semiconductor wafer; a second step of forming a stress cushioning layer on a plurality of semiconductor elements; a third step of forming an opening in the electrode pad of the stress cushioning layer and forming a notch wider than the width of the scribe line in the stress cushioning layer on the cutting scribe line of the semiconductor wafer; a fourth step of forming a lead wire portion extending from the electrode pad to the stress cushioning layer via the opening; a fifth step of forming a conductor protective layer which covers the stress cushioning layer and lead wire portion and has an external electrode connection window portion on the lead wire portion and a notch at the position corresponding to the notch of the stress cushioning layer; a sixth step of forming an external electrode in the external electrode connection window portion; and a seventh step of cutting the semiconductor wafer along the cutting scribe line, thereby obtaining a plurality of semiconductor devices in minimum units.
To accomplish the above object, the semiconductor device manufacturing method of the present invention has a first step of forming a plurality of semiconductor elements having an integrated circuit and an electrode pad on the circuit forming surface of a semiconductor wafer; a second step of forming a semiconductor element protective layer on a plurality of semiconductor elements; a third step of forming a first opening in the electrode pad of the semiconductor element protective layer and forming a notch wider than the width of the scribe line in the semiconductor element protective layer on the cutting scribe line of the semiconductor wafer; a fourth step of forming a stress cushioning layer on the semiconductor element protective layer; a fifth step of forming a second opening in the electrode pad of the stress cushioning layer and forming a notch at the position corresponding to the notch of the semiconductor element protective layer in the stress cushioning layer on the cutting scribe line of the semiconductor wafer; a sixth step of forming a lead wire portion extending from the electrode pad to the stress cushioning layer via the first and second openings; a seventh step of forming a conductor protective layer, which covers the stress cushioning layer and lead wire portion and has an external electrode connection window portion on the lead wire portion and a notch at the position corresponding to the notch of the stress cushioning layer; an eighth step of forming an external electrode in the external electrode connection window portion; and a ninth step of cutting the semiconductor wafer along the cutting scribe line, thereby obtaining a plurality of semiconductor devices in minimum units.
According to each feature mentioned above, each end face of the stress cushioning layer and conductor protective layer, or each end face of the semiconductor element protective layer, stress cushioning layer, and conductor protective layer in the end face area of each semiconductor element, is formed so as to be positioned inside the semiconductor wafer cutting scribe line and exposed within the range from the end face of each semiconductor element to the inside of the scribe line, so that when a semiconductor wafer is to be cut along the semiconductor wafer cutting scribe line, the semiconductor wafer can be cut by surely recognizing the positioning marks located on the semiconductor wafer, whereby defective semiconductor packages due to a displacement of the cutting position of each obtained semiconductor device can be eliminated.
Further, according to each feature mentioned above, when each semiconductor device is to be obtained by cutting a semiconductor wafer, the cut portion of each semiconductor device is formed to have a single-layer structure only of a semiconductor element; and, even if mechanical stress is generated at the time of cutting of the semiconductor wafer, the mechanical stress is just applied to the single-layer structure, so that a plurality of resin layers will not be peeled off by the mechanical stress.
Furthermore, according to each feature mentioned above, when each semiconductor device is to be mounted, even if thermal stress is generated due to great changes in the environmental temperature and the thermal stress is applied to a plurality of resin layers, a large mechanical stress is not applied to the plurality of resin layers when the semiconductor wafer is cut, so that the plurality of resin layers are hardly damaged, with the result that none of the plurality of resin layers will be peeled off or very little peeling will occur due to thermal stress.
As mentioned above, according to each feature mentioned above, the semiconductor devices will not be damaged at all or very little damage will occur due to application of mechanical stress and thermal stress, so that the reliability of the semiconductor devices can be enhanced, and the production yield rate of the semiconductor devices can be increased.